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Design and Analysis of Shift Register Using Pulse Triggered Flip-Flops and Pulsed Latches

Author(s):

K.Rajesh , SRI MITTAPALLI COLLEGE OF ENGINEERING; Mr. R.Bapannadora, SRI MITTAPALLI COLLEGE OF ENGINEERING

Keywords:

low power, area-efficient, flip-flop, pulsed clock, pulsed latch, pulse triggered, shift register

Abstract

Nowadays for each and every designing in VLSI era the power consumption plays a vital role. Low power has emerged as a principal theme in today’s electronics industry. The low power VLSI design has important role in designing of many electronic design systems. On designing any combinational or sequential circuits, the power consumption, implementation area, voltage leakage, and efficiency of the circuit are the important parameters to be considered initially. This paper proposes a low-power and area-efficient shift register using pulsed latches. The area and power consumption are reduced by replacing flip-flops with pulsed latches. This method solves the timing problem between pulsed latches through the use of multiple non-overlap delayed pulsed clock signals instead of the conventional single pulsed clock signal. The shift register uses a small number of the pulsed clock signals by grouping the latches to several sub shifter registers and using additional temporary storage latches. A 256-bit shift register using pulsed latches was fabricated using a 0.18 micro meter CMOS process with VDD=1.8V.

Other Details

Paper ID: IJSRDV4I70466
Published in: Volume : 4, Issue : 7
Publication Date: 01/10/2016
Page(s): 1010-1017

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