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Design and Analysis of Sleepy Instruction Caches for High Speed and Memory Efficient STT-RAM


Mr. S. Shanmuga Raju , Dr. N. G. P. Institute Of Technology; S. Remya, Dr. N. G. P. Institute Of Technology; S. Sathya, Dr. N. G. P. Institute Of Technology; S. Shiny G Deborah, Dr. N. G. P. Institute Of Technology; G. Soniya, Dr. N. G. P. Institute Of Technology


Sleepy Instruction Cache, Spin-Transfer Torque Random Access Memory (STT-RAM), Sub-Block, Cache Hierarchy, Write Amount


The motto of this proposal is based on efficient memory optimization concept. For high speed STT-RAM, the sleepy instruction caches is used not only for write amount aware, but also for efficient read address enable solutions. To allow the selection of STT-RAM in the implementation of cache memories, new cache hierarchy levels of managing policies are required for overcoming such drawbacks. In this, we evaluated several cache hierarchy management policies in the context of STT-RAM L1 caches and STT-RAM L2 caches. We also found that the non-exclusive policy is superior to non-inclusive and exclusive policies in terms of energy consumption and endurance. We also proposed this sleepy instruction caches with sub block-based management policy because the write energy consumption and endurance are proportional and inversely proportional to the amount of written data respectively.

Other Details

Paper ID: IJSRDV5I120437
Published in: Volume : 5, Issue : 12
Publication Date: 01/03/2018
Page(s): 1148-1150

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