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An Efficient Design for Low Power and Low Complex Full Adder using Ground Bounce Noise Reduction for Wireless Base Band Application

Author(s):

Saurabh Kumar Singh , St. Margaret Engineering College Neemrana; Mayank Sharma, St. Margaret Engineering College Neemrana

Keywords:

Ground Bounce, Sleep Transistor, DSCH, Leakage Current, Micro wind

Abstract

As if we saw that the technology comes into the nanometer range so that the ground bounce noise and noise immunity are becalmed very important factor of comparable importance to leakage current, active power, delay and area for the design and analysis and the design of complex arithmetic logic circuits. In this research thesis we have proposed A low leakage 1bit full adder cells for various mobile applications with very low ground bounce noise and a very good technique has been put forward with improved a new staggered phase damping technique for the further reduction in the peak of ground bounce noise. We also found that the noise immunity is carefully calculated and considered so that the significant value of the threshold current and low threshold voltage transition are becomes more susceptible to noise. We shows and put forward a new transistor resizing approach for 1bit full adder cells to determine how to optimize a size of sleep transistor which reduce the leakage power and ground bounce noise. The final simulation results shows that the output forwarded design also have a very effective 1bit full adder cells in terms of standby leakage power and an active powered, ground bounce noise and noise margin.

Other Details

Paper ID: IJSRDV5I120471
Published in: Volume : 5, Issue : 12
Publication Date: 01/03/2018
Page(s): 812-818

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