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A Literature Review on High Speed Area Efficient ALU using Different Energy Efficient Approaches

Author(s):

Rohit Kumar , UNIVERSITY INSTITUTE OF TECHNOLOGY ,AISECT UNIVERSITY ; Ravitesh Mishra; Ashish Chouhan

Keywords:

ALU, Xilinxs, VHDL, Verilog, Complexity, Size

Abstract

In this paper, Authors have presented the literature on coming up with of high speed, less area 64-bit ALU using economical techniques. The optimization of the projected style can be done by using the various techniques. The parameters speed and area of the projected style can be improved by using Carry Look Ahead Techniques. It also reduces the circuit quality. The ALU is a fundamental building block of central process unit of a laptop that is employed within the simplest microprocessors for purpose of maintaining timers. Previously, much economical design has been introduced for the style of low quality operation, but we tend to have given the attention to the carry look ahead and reversible gate techniques. The proposed style of ALU can performs the mathematical, logical, and shifting operations like Addition, Subtraction, Multiplication, Increment, Decrement, Logical AND, Logical OR, Logical XOR etc. in the computer. In this paper, the efficient modules of ALU are style using Xilinx package and simulation results can be verified on same platform exploitation check benches.

Other Details

Paper ID: IJSRDV5I120547
Published in: Volume : 5, Issue : 12
Publication Date: 01/03/2018
Page(s): 1078-1081

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