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FPGA Implementation Of Area Efficient Finite field Redundant Multipliers

Author(s):

RAGU B S T , KNOWLEDGE INSTITUTE OF TECHNOLOGY; S.Maragatharaj, KNOWLEDGE INSTITUTE OF TECHNOLOGY; N..Vijayanantham, KNOWLEDGE INSTITUTE OF TECHNOLOGY

Keywords:

Application-Specific Integrated Circuit, Galois Field, Finite Field Multiplication, Field Programmable Gate Array, High-Throughput, Digit-Serial, Redundant Basis

Abstract

Redundant Basis (RB) multipliers over Galois Field (GF) is a basic operation in modern cryptographic systems. Because of their negligible hardware budget for squaring and modular reduction. An improved recursive decomposition algorithm has been applied for Redundant Basis multiplication to get the high-throughput digit-serial presentation. Over effective forecast of Signal-Flow Graph (SFG) of the planned algorithm, an extremely regular Processor-Space Flow-Graph (PSFG) is obtained. The analysis and synthesis outcomes confirm the efficiency of planned multipliers over the present ones. The synthesis outcomes for Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) consciousness of the planned designs and present designs are compared. The high-throughput structures are the best among the corresponding designs, for Field Programmable Gate Array and ASIC implementation.

Other Details

Paper ID: IJSRDV5I31112
Published in: Volume : 5, Issue : 3
Publication Date: 01/06/2017
Page(s): 1427-1431

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