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Analysis of Shift Register using Flip-Flops and Pulsed Latches

Author(s):

Joyce Kamali D , Dr.Sivanthi Aditanar College of Engineering,Tiruchendur; Mr. A. Jeyapaul Murugan, Dr.Sivanthi Aditanar College of Engineering,Tiruchendur

Keywords:

Pulsed Laches, Flip-Flops

Abstract

Flip-flops and latches are the major power consuming memory element in Very Large Scale Integration digital circuits. This paper proposes a low power and delay efficient shift register using pulsed latches. The performances of memory elements are analyzed and their efficiency on power and delay are compared. The flip-flops which are chosen for comparison are explicit pulsed Data Close to output, Sense Amplifier Flip-flop, Power PC style Flip-flop and the latches which are chosen for comparison are Hybrid Latch Flip-flop, Transmission Gate Pulsed Latch and Static differential Sense Amp shared Pulse Latches .As a result of comparison, Static differential Sense Amp shared Pulse Latches is the efficient latch. So the 16 bit shift register is designed with the help of Static differential Sense Amp shared Pulsed Latches. Simulation is done using Tanner EDA tool in 180 nm technology. The power consumption is 0.23W at a 100MHz clock frequency.

Other Details

Paper ID: IJSRDV5I40213
Published in: Volume : 5, Issue : 4
Publication Date: 01/07/2017
Page(s): 251-254

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