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Design of 4-Bit Flash ADC using 180 nm Technology

Author(s):

Sonu Kumar , DCRUST MURTHAL; Rekha Yadev, DCRUST MURTHAL

Keywords:

Flash ADC, Comparator, Priority Encoder, Cadence Virtuoso, Power Dissipation, Delay

Abstract

Analog to digital converter (ADC) is an integral part of communication and a crucial asset for digital signal processing. ADCs, find a wide variety of applications in today’s digitized world. Flash ADCs are fastest among all the types of ADCs discovered so far. A 4-Bit Flash ADC has been designed using Cadence Virtuoso in 180nm CMOS technology. ADC has been developed using two stage open loop comparators, a priority encoder. The analog output of each comparator depends upon the input, the reference voltage supplied to the priority encoder, and finally, the digital output obtained. Parameters calculated are bandwidth (Mhz), resolution (mV) and power consumption (mW) are 79.53, 50, .005 respectively for comparator. For ADC calculated parameters are DNL, Delay(ms), Maximum input Frequency(Mhz), Rise time(ns), Fall time(ns), power consumption (mW) are .029, 1.9, 87.19, 15.89, 3.87,368.

Other Details

Paper ID: IJSRDV5I41078
Published in: Volume : 5, Issue : 4
Publication Date: 01/07/2017
Page(s): 1179-1181

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