High Impact Factor : 4.396 icon | Submit Manuscript Online icon |

Non Redundant Radix-4 Signed Digit Encoding DSP Accelarator

Author(s):

A. Krishna Veni , SUDHEER REDDY COLLEGE OF ENGINEERING AND TECHNOLOGY; P. Sayanna, SUDHEER REDDY COLLEGE OF ENGINEERING AND TECHNOLOGY

Keywords:

NR4SD, Pre-Encoded Multiplier, FCU, Carry Save Form, Modified Booth Encoding

Abstract

DSP accelerator has very prominent role in digital signal processing applications. Acceleration mainly performed in the application specific integrated circuit devices. DSP accelerator has perform various arithmetic operations to improve the performance of the Acceleration proposed technique is implemented i.e. NR4SD.i.e.Non Redundant Radix-4signed digit encoding technique, it has high performance compared with the modified booth algorithm and also it has lass decoding time for data transmission. In this paper the complete design of DSP accelerator is designed with NR4SD technique to improve the area, de-lay and power consumption. It has implemented with the verilog HDL and synthesize and simulated with the XILINX 14.5 ISE standard.

Other Details

Paper ID: IJSRDV5I50974
Published in: Volume : 5, Issue : 5
Publication Date: 01/08/2017
Page(s): 968-971

Article Preview

Download Article