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Design of 32-Bit Multiplier using Reversible Logic Technology Based on Urdhva Tiryakbhyam Sutra




Reversible Logic and Gates, Reversible Multiplier Circuit (RMC), Partial Product, Vedic Mathematics, Urdhva Tiryakbhyam, RLC, Compressor


In this paper the most significant aspect of the proposed method is that, the developed multiplier architecture is based on vertical and crosswise structure of Ancient Indian Vedic Mathematics. As per this proposed architecture, for two 32-bit numbers; the multiplier and multiplicand, each are grouped as 16-bit numbers so that it decomposes into 16×16 multiplication modules. It is also illustrated that the further hierarchical decomposition of 8×8 modules into 4×4 modules and then 2×2 modules will have a significant Verilog HDL(hardware description language) coding of for 32x32 bits multiplication and it was observed that the parameters like Hardware Complexity, power and Delay are improved over other Reversible multipliers. The design is simulated, synthesized and power estimation was done using 14.3 version Xilinx tools.

Other Details

Paper ID: IJSRDV5I51429
Published in: Volume : 5, Issue : 5
Publication Date: 01/08/2017
Page(s): 1729-1733

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