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Design of Double Gate Heterojunction TFET for Low Power Applications

Author(s):

Prabhat Tamak , NITTTR CHANDIGARH; Rajesh Mehra, NITTTR, CHANDIGARH

Keywords:

Gate Dielectric, BTBT, MOSFET, Double Gate (DG), Tunnel Field Effect Transistor, CMOS

Abstract

Due to various problems which are exist with the scaling of MOSFET (Metal Oxide Semiconductor FET) devices such as short channel effects, drain induced barrier lowering (DIBL) and saturation of velocity are limits to the performance of MOSFET. To overcome the existing problems a new device Tunnel FET is alternative to the MOSFET. This paper, propose a design for a double gate Hetero-junction tunnel field effect transistor (DG Tunnel FET). In this work, using the calibrated 2-D TCAD simulation, we demonstrate that the ON current (ION) and OFF state current (IOFF) for the double gate Hetero-Junction Tunnel FET shows the improvement with a silicon channel and SIO2 as a gate dielectric. DG Tunnel FET is explored by using the practical design parameters which shows ON-state current 13.12μA/μm and the OFF current achieved is l.68pA/μm for a gate voltage of 1V which specify that better power switch performance.

Other Details

Paper ID: IJSRDV5I60023
Published in: Volume : 5, Issue : 6
Publication Date: 01/09/2017
Page(s): 40-44

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