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The Design and Simulation of Split Radix FFT Processor using Multi-Bit FlipFlop for Power Reduction

Author(s):

Bitta Balaji , Annamacharya Institute of technology and sciences; P. Syamala Devi, Annamacharya Institute of technology and sciences

Keywords:

Address Generation, Low Power, Radix-2, Split-Radix Fast Fourier Transform (SRFFT), MBFF, SFLP SRAM, Twiddle Factors

Abstract

Fast Fourier transform (FFT) is one of the most important and fundamental algorithm in digital signal processing area. Split radix fast Fourier transform (SRFFT) algorithm requires the least number of multiplications and additions among all the known FFT algorithms, which contribute to overall system power consumption. In the design of such processors, modified radix-2 Shared memory architecture can be used instead of Pipelined FFT architecture. In contrast Shared memory based architecture requires least amount of hardware resources at the expense slower throughput. To implement this Shared memory architecture, Multi-Bit FlipFlop (MBFF) and Superfast low power SRAM (SFLP SRAM) cell are required. The SRFFT can be computed by using a modified radix-2 butterfly unit. The butterfly unit exploits the multiplier gating technique to save dynamic power. In addition, two address generation algorithm are developed for both real and imaginary parts of twiddle factors. In simulation results the power is measured by T-Spice using Tanner tool. Hence the proposed architecture will save more power when it comes to larger points of FFT.

Other Details

Paper ID: IJSRDV5I60177
Published in: Volume : 5, Issue : 6
Publication Date: 01/09/2017
Page(s): 343-346

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