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Design of SRAM with Negative Capacitance Circuit


Prof. G. A. Waghmare , STC,SERT,Khamgaon; Prof. G. M. Kathalkar, STC,SERT,Khamgaon


SRAM, Process Variation, Read Access Failure, Negative Capacitance Circuit


Modern day portable devices and ICs demand memory with large size for storage and data manipulation. SRAM having high performance and large size with low power and area makes the design complicated. Due to scaling of CMOS the effect of process variation increases which spread the delay in circuit. The overall effect of process variation in designing SRAM of large size with low area in nanometer technology causes the SRAM cell to functionally fail. Functional failure includes read access failure, write failure. In this paper SRAM of size 512 is design which uses negative capacitance circuit to improve the readability of SRAM. Use of negative capacitance circuit reduces the bit line capacitance which results in improvement of SRAM readability. 512 SRAM cells is design in 180nm technology using 0Tanner EDA tool 13.0.

Other Details

Paper ID: IJSRDV5I60320
Published in: Volume : 5, Issue : 6
Publication Date: 01/09/2017
Page(s): 586-589

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