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Analysis of High Performance and Low Power Shift Registers using Pulsed Latch Technique


Neha Sharma , Geetanjali Institute of Technical Studies, Udaipur, Rajasthan; Vijendra K. Maurya, Geetanjali Institute of Technical Studies, Udaipur, Rajasthan


Shift Registers, Low Power, Pulsed Latch, D Flip Flop


In this work, the performance of shift registers is improved using pulsed latch technique. In high speed and low power VLSI applications where heavy pipelining is required, low power edge triggered flip flops are used. The replacement o flip flop with pulsed latch has shown great success in low power VLSI applications. The proposed circuit has been designed using Tanner Tools v 14.1 in CMOS technology. The pulse latch technique reduces the power consumption significantly in the designed circuit and there is also an improvement in power delay product. The proposed circuit also require less number of transistors for its implementation as compared to conventional version.

Other Details

Paper ID: IJSRDV5I70182
Published in: Volume : 5, Issue : 7
Publication Date: 01/10/2017
Page(s): 319-323

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