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A Review on High Speed CRC Encoder and Decoder Based on FPGA

Author(s):

Shraddha Dnyaneshwarrao Datir , P.R. POTE COLLEGE OF ENGINEERING AND MNAGEMENT, AMRAVATI; Dr. R.D. Ghongade (HOD), P.R.POTE COLLRGR OF ENGINEERING AND MANAGEMENT ,AMRAVATI

Keywords:

Cyclic Redundancy Check (CRC), Encoder, Decoder, Field Programmable Gate Array (FPGA), Serial CRC, Parallel CRC

Abstract

Cyclic redundancy check (CRC) technique is one of the most efficient error detection method, which used to detect single and burst errors. CRC method adds redundancy bits to the original data. The reminder of division between original message and selected polynomial is represents redundancy bit. At the receiver side, the received data can be recognized as valid or not. Generally speaking, (CRCs) are used to detect errors from noise in digital data transmission. The technique is also sometimes applied to data storage devices, such as a disk drive. They also have been turned to verify the integrity of files in a system in order to prevent tampering and suggested as a possible algorithm for manipulation detection codes .A Cyclic Redundancy Check (CRC) is the remainder or residue of binary division of a potentially long message, by a CRC polynomial. Per packet operation is necessary for IP protocol, design a new efficient technique using FPGA in case of CRC .This approach is memory efficient and operate at high speed, since most of method currently employed based on look up table consume more time ,more space and also there will be a ROM which stores the look up table. This paper presents high speed CRC encoder and decoder using FIELD PROGRAMMABLE GATE ARRAY, to increase throughput pipeline method is used.

Other Details

Paper ID: IJSRDV6I120136
Published in: Volume : 6, Issue : 12
Publication Date: 01/03/2019
Page(s): 196-199

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