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Zipper Circuit for Low Power and High Speed Applications in VLSI Design

Author(s):

G Sivaiah , Ravindra Collage of Engineering for Women,Kurnool; T Kishore, Ravindra Collage of Engineering for Women,Kurnool

Keywords:

Zipper, CMOS, NP Domino Logic, Monotonicity

Abstract

A low power low cost CMOS NP Domino logic is design. The NP Domino logic designs require fewer transistors and are compatible with full Domino logic. The performance of NP Domino logic is also better compared to the standard Domino logic implementations. Dynamic domino logic are very good but had many challenges like monotonicity, leakage, charge sharing and noise problems. These problems are totally eliminated in the CMOS NP Domino logic which is also known as Zipper circuits without any penalty in performance or silicon area utilization. This paper compares NP Domino logic with static CMOS and domino logic design implementations.

Other Details

Paper ID: IJSRDV6I120223
Published in: Volume : 6, Issue : 12
Publication Date: 01/03/2019
Page(s): 341-344

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