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Energy Efficient Single Port 64-Word 8-Bit Memory

Author(s):

Indhu S , MAHENDRA ENGINEERING COLLEGE; Giri K, MAHENDRA ENGINEERING COLLEGE; Senthilkumaran V, MAHENDRA ENGINEERING COLLEGE

Keywords:

March tests, Complete Linear Feedback Shift Register, Configurable Complete Linear Feedback Shift Register, Test Pattern Generators

Abstract

Presented here is a memory design project using Verilog hardware description language (HDL). The single-port memory is basically the design as per your defined specifications. Then, as per the specified width and depth, define the memory block that can also be verified using field programmable gate array (FPGA) boards. Low power and low area Static Random-Access Memory (SRAM) is essential for System on Chip (So C) technology. Dual-Port (DP) SRAM greatly reduces the power consumption by full current-mode techniques for read/write operation and the area by using Single-Port (SP) cell. An 8bit DPSRAM is proposed in this study. Negative bit-line technique during write has been utilized for write-assist solutions. Negative voltage is generated on-chip using capacitive coupling. The proposed circuit design topology does not affect the read operation for bit interleaved architectures enabling high-speed operation. Designed in XILINX ISE 14.4 Simulation results and comparative study of the present scheme with state of-the art conventional schemes proposed. show that the proposed scheme is superior in terms of process variations impact, area overhead, timings and dynamic power consumption. The proposed negative bit line technique can be used to improve the write ability of 6 T Single- Port (SP) as well as 8 T DP and other multiport SRAM cells.

Other Details

Paper ID: IJSRDV6I120455
Published in: Volume : 6, Issue : 12
Publication Date: 01/03/2019
Page(s): 582-585

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