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8-Bit Universal Shifter using Verilog

Author(s):

Sarasvathi S , MAHENDRA ENGINEERING COLLEGE; Saraswathi S, MAHENDRA ENGINEERING COLLEGE; Giri K, MAHENDRA ENGINEERING COLLEGE

Keywords:

Adiabatic; Low Power; DFAL; Shift Register

Abstract

8 Bit Universal Shift Register is a register which can be configured to load and/or retrieve the data in any mode (either serial or parallel) by shifting it either towards right or towards left. Since power dissipation is a critical factor many low power dissipation techniques have been proposed but most of these techniques have some trade-offs. Adiabatic logic technique as compared to that of a conventional CMOS technique shows promising results. A type of adiabatic technique, DFAL (Diode Free Adiabatic Logic), has been studied in this paper and NOR gate, NAND gate, XOR gate, D Flip-Flop and Universal Shift Register have been designed using this configuration. DFAL circuits are analyzed based on transistor count, power dissipation and delay. All the circuits are simulated in Pyxis (Mentor Graphics) 180nm technology at1.8V.

Other Details

Paper ID: IJSRDV6I120457
Published in: Volume : 6, Issue : 12
Publication Date: 01/03/2019
Page(s): 615-618

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