CMOS Design and Analysis of Receiver System in Satellite Communication using 180 nm technology

This project describes the complete design of a low-cost 14 GHz Receiver front-end in 180 nm technology. It covers the topics of a system plan, designs of building blocks, designs of application-boards and real environment tests. A homodyne architecture with a 500 MHz IF. The design of a LNA in Radio Frequency (RF) circuit requires the trade-off in many importance characteristics such as gain, Noise Figure (NF), stability, power consumption and complexity. Expressions developed will help circuit and system designers to come to an optimum power consumption versus performance trade-off. An RF receiver front-end Receiver systems is designed. The receiver occupies only 0.35 mm2 in a 0.18 μm CMOS process, consists of a low-noise amplifier, downconverter and a low pass filter. The measured receiver gain is 21 dB, Noise Figure is less than 5 dB, input IIP3 is -5 dBm and the receiver consumes 19.5 mW from a 1.8V supply. The receiver covers all the bands from 13 GHz to 15 GHz.