Design and Simulation of Arithmetic and Logic Unit with Status Register using Verilog-HDL |
Author(s): |
| Harish Nimje , shri shankaracharya institute of proffessional management and technology; Mohit Kushwaha, shri shankaracharya institute of proffessional management and technology; Vinod Asdev, shri shankaracharya institute of proffessional management and technology; Garima Sharma, shri shankaracharya institute of proffessional management and technology |
Keywords: |
| ALU, MSB, RTL |
Abstract |
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In this paper an arithmetic and logic unit is designed of 32 bits and in addition its status register also added in this design. Its design is done by Verilog which is a hardware descriptive language. In this design arithmetic operations like addition, subtraction, multiplication and division is done and it also includes bit wise logical operations like and, or, xor. The flag of the status register is get manipulated according to the output of the ALU. |
Other Details |
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Paper ID: IJSRDV6I21888 Published in: Volume : 6, Issue : 2 Publication Date: 01/05/2018 Page(s): 2841-2843 |
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