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Design and Implementation of Single Precision Floating Point Multiplier using DADDA Architecture with FPGA

Author(s):

Bharath R B , Dr. Ambedkar Institute of Technology; Aravind S, Dr. Ambedkar Institute of Technology; Chinnaraj Nayak, Dr. Ambedkar Institute of Technology; Ganesh Shetti, Dr. Ambedkar Institute of Technology; Nithyashree S, Dr. Ambedkar Institute of Technology

Keywords:

Single-Precision Floating Point Multiplication, DADDA Reduction, Wallace, Modified Booth Encoding

Abstract

This paper work is devoted for the design and simulation of Single-Precision Floating Point Multiplier for signed and unsigned numbers using DADDA architecture. The multiplication operation is present in most parts of a digital system or digital computer, most notably in signal processing, graphics and scientific computation. With advances in technology, several techniques have been proposed to design multipliers, which offer high speed, low power consumption and requires lesser area. Thus making them suitable for various high speeds, low power compact VLSI implementations. The Design employs Combination of different adders and fast Compressors. The Carry Save Compressors (CSC) tree and the final Carry Propagate adder (CLA) chain is used to speed up the multiplier operation. Since signed and unsigned multiplication operation is performed by the same multiplier unit the required hardware and the chip area reduces and this in turn reduces power dissipation and cost of a system. Verilog coding of multiplier for signed and unsigned numbers using DADDA Algorithm for 32X32 bit multiplication following the Standard IEEE Format and their FPGA implementation by Xilinx Synthesis Tool on Spartan 6 kit have been done. The output has been displayed on LED of Spartan 6 kit. The multiplier structure is also designed in Cadence Software with 180nm technology.

Other Details

Paper ID: IJSRDV6I22072
Published in: Volume : 6, Issue : 2
Publication Date: 01/05/2018
Page(s): 3545-3548

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