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Performance Analysis of Shift Registers using Pulsed Latch Technique

Author(s):

Bhuvaneshwari. S , SRI ESHWAR COLLEGE OF ENGINERING; Anand Kumar .V, SRI ESHWAR COLLEGE OF ENGINERING

Keywords:

Flip-Flops, Pulse Triggered, CMOS, Pulse Latch, Power Consumption, Low-Power, VLSI, Delay, Shift Register

Abstract

In modern VLSI circuit design, the most important aspects is to minimal power consumption and obtain optimal efficiency in any of the electrical device. This work presents a 4 type of shift register and using pulsed latch technique instead of d proposed flip-flop design style. Generally, the advantages of both the latches and flip-flops in pulse latch technique are analysed to achieve high speed and lower power consumption. In this work, pulsed latch technique of d proposed flip flop has been used to analysis the performance of various shift registers. In this different types of proposed shift register using d proposed flip flop pulse latch technique are analysed and comparison results are displayed , All the proposed shift registers have been designed in 90 nm CMOS technology and their functionality have been verified using Microwind tool. From this work, it has been analysed that, layout size, transistor count, delay and power.

Other Details

Paper ID: IJSRDV6I40155
Published in: Volume : 6, Issue : 4
Publication Date: 01/07/2018
Page(s): 268-270

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