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Design and Comparative Analysis of High Speed and Low Power 8x8 bit Radix-4 Booth Multiplier

Author(s):

Mr. Bharat H. Nagpara , C. U. Shah College of Engineering and Technology,; Mr. S. D. Madhar, C.U.Shah Technical Institute of Diploma Studies,

Keywords:

Booth Multiplier Algorithm, Radix 4 Modified Booth Multiplier, Simulation Results, Comparison

Abstract

Multiplication is essential operation for any high speed digital logic system design, digital signal processors or control system. Primary issues in design of multiplier are area, delay, and power dissipation. Many design architectures and techniques have been developed to overcome these issues. This paper mainly presents radix-4 booth multiplier using Booth encoder, Booth decoder, Sign extension and Carry Look-ahead Adder (CLA) blocks. Keeping in mind that power dissipation and delay are the primary factors for multiplier and it should be improved in the design. The design has been implemented using PTM 45nm CMOS technology at 1.0v supply voltage in TANNER EDA V.15 tool. The results are compared with previously reported papers.

Other Details

Paper ID: IJSRDV6I40559
Published in: Volume : 6, Issue : 4
Publication Date: 01/07/2018
Page(s): 720-722

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