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Design & Implementation of 16-Bit RISC Processor


Sivakumar Ogirala , Geethanjali College of Engineering and Technology; P. V. S. K. Pavan, Geethanjali College of Engineering and Technology; Mithin Varghese, Geethanjali College of Engineering and Technology; T. Madhulika Reddy, Geethanjali College of Engineering and Technology


16-bit RISC Processor


Objectives: This paper presents the design of a 16 bit Reduced Instruction Set Computing (RISC) processor. We have used modified Harvard architecture that uses separate memories for its instruction & data memory response where as in the other architecture by von Neumann, has only one shared memory for instruction and data, with one data bus and address bus with between data memory & processor memory. It is pipelined to a depth of 5 stages with stages corresponding to: Instruction Fetch, Instruction Decode and Register Fetch, ALU Operation, Memory Operation, and Register File Write. Findings: Various functional blocks of the processor such as the Control Unit, Instruction Decoder, Instruction Register unit and Arithmetic and Logical Unit (ALU) are designed using the Cadence tool.

Other Details

Paper ID: IJSRDV6I40564
Published in: Volume : 6, Issue : 4
Publication Date: 01/07/2018
Page(s): 1296-1298

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