Design and Implementation of MIPS Processor |
Author(s): |
Jitendra Sen , VNS; Anil Khandelwal, VVNS group of institution Bhopal |
Keywords: |
MIPS, VHDL, Instruction Set, ASIC |
Abstract |
The implementation of 16 bit RISC processor with microprocessor without interlocked pipeline stages MIPS) is presented. It was implemented in VHDL so as to reduce the instruction set present in the programmable memory. As the result the processor will contain the necessary logics for the implementation that requires fewer gates to be synthesized in the programmable matrix and has the capability to increase the speed of the target processor. |
Other Details |
Paper ID: IJSRDV6I60007 Published in: Volume : 6, Issue : 6 Publication Date: 01/09/2018 Page(s): 33-36 |
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