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Area-Efficient and Minimal Power Constituted on Shift Register using Pulsed Latches

Author(s):

Juweria Begum , Siddhartha College of Engineering; Immidisetty Venkata Prakash, Siddhartha College of Engineering

Keywords:

Area-Efficient, Flip-Flop, Pulsed Clock, Pulsed Latch, Shift Register

Abstract

The Shift Register is another type of sequential logic circuit that can be used for the storage or the transfer of data in the form of binary numbers. A power-efficient shift register utilizing a new flip-flop with a pulse-triggered structure is presented in this paper. The proposed flip-flop has features of high performance and low power. The key idea was to design in various performance aspects provide a signal feed through from input source to the internal node of the latch, which would facilitate extra driving to shorten the transition time and enhance both power and speed performance. The design was intelligently achieved by employing a simple pass transistor. The proposed design successfully solves the long discharging path problem in conventional explicit type pulse-triggered FF (P-FF) designs and achieves better speed and power performance. Based on post-layout simulation results using CMOS 90-nm technology. The best power-delay-product performance in seven FF designs under comparison. Its maximum power saving against rival designs is up to 37.4%.Compared with the conventional transmission gate-based FF design.

Other Details

Paper ID: IJSRDV6I60198
Published in: Volume : 6, Issue : 6
Publication Date: 01/09/2018
Page(s): 251-255

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