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A Flip Flop on the Dual Edge & Minimal Power Constituted on Feed of Signal


Achyuth Achar C , Siddhartha College of Engineering; Immidisetty Venkata Prakash, Siddhartha College of Engineering


Dual Edge Triggered, Flip Flop, High Speed, Low Power, Static D Flip Flop


In this paper a low-power double-edge triggered static flip-flop (DETSFF) suitable for low-power and high performance applications is presented. The designed DETFF is verified at GPDK 180nm-1.8V CMOS technology. Comparison with some of the latest DETFFs shows that the proposed DETSFF can achieve the lowest power consumption, lowest clock to Q delay and thus Power-delay-product (PDP). Moreover, the proposed DETSFF comprises of only 15 transistors hence requires lesser number of transistors and thus requires lesser overall silicon area.

Other Details

Paper ID: IJSRDV6I60248
Published in: Volume : 6, Issue : 6
Publication Date: 01/09/2018
Page(s): 301-304

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