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FPGA Implementation of Decimation Filter using Canonic Signed Method

Author(s):

Ku. Rupali B. Sawai , Dr. RGIT&R Amravati, India; Dr. R. M. Deshmukh, DR. RGIT&R Amravati, India

Keywords:

Decimation Filter, CIC Filter, FIR Filter, FPGA, Half Band Filter, MATLAB, Xilinx

Abstract

The hearing aid decimation filter is one of the technique employed with the help of FPGA simulation in which the problems of hearing loss person are considered and provides a better solution for hearing aid in quite as well as in whisper conditions for clear hearing. The design of decimator filter requires a set of filters for hearing aid applications that gives reasonable signal for the concerned type of hearing loss. Using a variable bandwidth filter, helps a person with hearing loss to listen and communicate by making sounds audible and clearer. The design of variable bandwidth filter is carried out for gain, such that, the different bands combine to give a frequency response that closely matches with audiogram. The technique employed for the design of the filter is Canonic Signed Digit (CSD) representation. The higher sampling rate of the signal is decimated to low sampling rate by implementing the filter using the multi rate a set of selected bandwidths. The main aim of the paper is to analyse and simulate the decimation filter using MATLAB. It is then simulated with ISE software to analyse a frequency response of a filter at particular level of frequency. Minimum frequency of a person hearing is usually considered to be 20 Hz whereas the maximum limit is 20 kHz, but the ear is more sensible to audio from 1 KHz to 4 KHz. Thus, it is beneficial to design a deaf aid application that operates in the desired range of frequency and makes use of oversampling concept.

Other Details

Paper ID: IJSRDV7I21228
Published in: Volume : 7, Issue : 2
Publication Date: 01/05/2019
Page(s): 1448-1451

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