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High Speed Low Power MAC Design using Parallel Adders and Multipliers

Author(s):

P. Kalyani , TKR College of Engineering and Technology; Y. Rachana, TKR College of Engineering and Technology; R. Soumya, TKR College of Engineering and Technology; M. Veeranna, TKR College of Engineering and Technology

Keywords:

MAC Design, Parallel Adders, Multipliers

Abstract

Multiply-Accumulate unit (MAC) is an important module in high performance applications. It is a fundamental block in computing devices especially digital signal processor. We performing a MAC designs with a new approach to parallel multiplier design by using parallel 1s counter to accumulate the binary partial product bits and carry save adder for high frequency operation is implemented of pipelined adder. It has a delay of only one full adder and one D-flipflop. To operate the circuit with lowest possible active power consumption, we propose a preliminary automatic supply and novel power reduction technique. Design is simulated and results are verified using cadence 45nm technology.

Other Details

Paper ID: IJSRDV7I21462
Published in: Volume : 7, Issue : 2
Publication Date: 01/05/2019
Page(s): 1812-1814

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