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FPGA Implementation of the Hybrid Model of Direct Digital Synthesizer (DDS) using LUT

Author(s):

Dasharathprasad Kailashnath Gupta , DKTE TEXTILE and ENGINEERING INSTITUTE Ichalkaranji; Mahesh K. Patil, DKTE TEXTILE and ENGINEERING INSTITUTE Ichalkaranji; Niraj B. Kapase, DKTE TEXTILE and ENGINEERING INSTITUTE Ichalkaranji; Santosh P. Salgar, DKTE TEXTILE and ENGINEERING INSTITUTE Ichalkaranji; B. N. Sachidanand, DKTE TEXTILE and ENGINEERING INSTITUTE Ichalkaranji

Keywords:

DDS; FPGA Implementation; Phase Accumulator; ROM; Xilinx14.1; VHDL; LUT

Abstract

The DDS have been experimentally implemented in Field Programmable Gate Array (FPGA) that synthesis the waveforms like sine wave, triangular, Saw tooth and Square wave using Look up Table (LUT). A Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) based ROM is designed using embedded RAM of the Xilinx Spartan - 6 FPGA chip. A VHDL based counter is also designed which works as address generator to continuously supply the address of ROM to read the stored sample values from the LUT. The digital part consists of a Phase Accumulator (PA) and a LUT. The 16-bits Phase Accumulator is implemented by means of a register along with an adder and feedback loop. LUT is implemented using VHDL code. The size of LUT is reducing by storing quarter of sine wave in the ROM. This design was tested with various tuning frequencies and the result shows that the output frequency is directly proportional to the tuning input frequency. The sample values are converted into continuous signals using a Digital to Analog Converter (DAC). The VHDL program is downloaded into FPGA chip using JTAG in Xilinx Integrated Software Environment (ISE) tool. The simulation results of VHDL based ROM with address generator is shown in the form timing diagram obtained using ModelSim software. Experimental result of generation of sinusoidal waveform is also presented. FPGA development board has 100MHz on board clock generator. Since we are using FPGA as a hardware part, in future easily upgrade the signal generator by altering the VHDL program for FPGA design. Estimated power consumption of the FPGA based design excluding the DAC is found to be 240mW.

Other Details

Paper ID: IJSRDV7I40766
Published in: Volume : 7, Issue : 4
Publication Date: 01/07/2019
Page(s): 762-765

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