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Design of Receiver Continuous Time Linear Equalizer for High Gain

Author(s):

Mohini Deore , SCOE,Pune; Prof. V. G. Raut, SCOE,Pune

Keywords:

CTLE, CMOS, CML, Desrializer, MOSFET, Serializer

Abstract

This paper presents a design of continuous-time linear equalizer for 4 dB equalization at 1GHz frequency and for process corners the testing of MOSFET device is presented. One of the key components in the design of the digital SERIALIZER / DESRIALIZER circuit channels is the continuous time linear equalizer (CTLE), which compensates for the high frequency loss of electric channels. The objective is to design the continuous linear time equalizer circuit and to analyze the circuit performance. For the project all the circuits are being implemented in 45nm CMOS technology.

Other Details

Paper ID: IJSRDV7I50010
Published in: Volume : 7, Issue : 5
Publication Date: 01/08/2019
Page(s): 32-34

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