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Design and Implementation of High Performance 5T SRAM

Author(s):

Kunal A Wankhade , KGIET DARAPUR; Kajal Gaykwad, DRGITR AMRAVATI

Keywords:

5T SRAM, 6TSRAM

Abstract

The paper describes the thorough overview of DRAM. The review discusses basic introduction of DRAM, DRAM architecture and its support circuitry. The paper also focuses on the study of four transistor DRAM cell, two transistor DRAM cell and one transistor DRAM cell. Read and write operations of different types of DRAMs are explained with help of control signal waveform. The comparison between two basic types of memories i.e. SRAM and DRAM is also discussed in the paper. Semiconductors memories are most important in todays aera. As the scaling large memories are fabricated on a single chip. It is possible to store large amount of data on and retrieve it at very high speed. The design of more memories on a single chip which increases power dissipation. The proposed design based on 5T SRAM with standby startup circuit which reduces power dissipation and reduction in leakage current. The circuit is design in 45nm CMOS technology file.

Other Details

Paper ID: IJSRDV7I70015
Published in: Volume : 7, Issue : 7
Publication Date: 01/10/2019
Page(s): 26-28

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