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ASIC Design of High speed FSM based DDR4 SDRAM controller for fast Interface

Author(s):

Nitish Kumar Vishwakarma , GGITS jabalpur; Prof. Sunil Shah, GGITS jabalpur

Keywords:

SDRAM, DDR, FPGA, RTS

Abstract

The goal of this thesis is to explore the options for a predictable SDRAM controller for the FPGA platform. The variable SDRAM access latencies pose some challenges for its effective use in RTS, while the many-core FPGA platform creates a new context for rethinking the previous results and finding the new solutions for external memory access. The simple working prototype of the single-port SDRAM controller is implemented and integrated with the processor. Several options for multi-port arbitration are considered, and proposal is made for arbitration and interconnects in FPGA project. Xilinx ISE is been used for development of the SDRAM controller.

Other Details

Paper ID: IJSRDV8I120003
Published in: Volume : 8, Issue : 12
Publication Date: 01/03/2021
Page(s): 19-22

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