Analysis and Perform an convolutional encoder |
Author(s): |
| Tarunkumar C. Lad , SVNIT, SURAT, India; Patel Pratik J., CGPIT, Maliba Campus, UTU |
Keywords: |
| Forward Error correction, Xilinx, RTL simulation, SPRTAN 3E FPGA. |
Abstract |
|
this paper focused on the two different system of the convolutional encoder. We have to present a Spartan 3E field programmable gate array (FPGA) implementation of Convolutional Encoder with a constraint length of 3 and two different code rate 1/2 and 1/3. The purpose of a convolutional encoder is to a single input and generates encoded outputs. In this paper analysis and perform different type of system in the convolutional encoder. The system implication in VHDL and also simulated and synthesizes using Xilinx for RTL design. |
Other Details |
|
Paper ID: IJSRDV1I10049 Published in: Volume : 1, Issue : 10 Publication Date: 01/01/2014 Page(s): 2256-2259 |
Article Preview |
|
|
|
|
