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Survey of Optimization of FFT processor for OFDM Receivers


Nirav Chauhan , Kalol Institute of Technology & Research Centre, Kalol, Ahmedabad, Gujarat, India; Dr. Shruti Oza, Kalol Institute of Technology & Research Centre, Kalol, Ahmedabad, Gujarat, India; Dr. Kiran Parmar, L.D. College of Engineering, Ahmedabad, Gujarat, India


FFT, IFFT, DFT, Pipelining, Parallel Processing, Orthogonal Frequency Division Multiplexing (OFDM), Coordinate Rotation Digital Computer (CORDIC).


In the last few years wireless communications have experienced a fast growth due to the high mobility that they allow. However, wireless channels have some disadvantages like multipath fading that make them difficult to deal with. A modulation that efficiently deals with selective fading channels is OFDM. There are a large number of FFT algorithms and architectures in the signal processing literature. Therefore, the state of art algorithms and architectures should be analyzed and compared. Based on different algorithms and architectures, different power consumptions, area and speed of the processor will be achieved. So their ASIC suitability should be analyzed and the effort should be focused on the choosing algorithms and architectures and optimization. In this paper FFT Processor with Pipelined Architecture and CORDIC based ROM-free twiddle factor generator is proposed. The proposed algorithm and architecture should be validated by MATLAB simulation before implementation. After that, it is implemented on DSP Processor kit with Code Composer Studio. The synthesis results will be compared with other published FFT processor results.

Other Details

Paper ID: IJSRDV1I2007
Published in: Volume : 1, Issue : 2
Publication Date: 01/05/2013
Page(s): 74-77

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