A comprehensive study on Implementing of 10bit Two step Flash ADC |
Author(s): |
| Nehal Parmar , GTU Ahmedabad, Gujarat, India; Rakesh G. Trivedi, GTU Ahmedabad, Gujarat, India |
Keywords: |
| Flash ADC,DAC,Chip,power |
Abstract |
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This paper proposes a 10bit two step flash ADC.As the CMOS technology continues to scale down, signal processing is favourably done in digital domain, which requires Analog to digital converters (ADCs) to be integrated on-chip. Among various ADC architectures, the two step flash ADC architecture is the best suited for low power and 10 bit resolution. To decrease the area, power consumption, and cost while maintaining 10bit accuracy, the architecture is divided into coarse flash ADC and fine flash ADC connected through current steering Digital to analog converter (DAC) and residue amplifier. To get the best performance the coarse convertor of 5bit and the fine convertor of 5bit are chosen. The comparator design is done with optimum power and area. Intermediate state accuracy increased by thermometer coded current steering DAC. |
Other Details |
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Paper ID: IJSRDV1I2064 Published in: Volume : 1, Issue : 2 Publication Date: 01/05/2013 Page(s): 318-322 |
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