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Five Port Router Architecture


A. Umma Maheswari , Siddharatha Institute of Engineering and Technology; E. Nagaraju, Siddharatha Institute of Engineering and Technology


router, packets, FPGA, RTL, IP.


In this paper we attempt to give a networking solution by applying VLSI architecture techniques to router design for networking systems to provide intelligent control over the network. Networking routers to have limited input/output configurations, which we attempt to overcome by adopting bridging loops to reduce the latency and security concerns. Other techniques we explore include the use of multiple protocols. We attempt to overcome the security and latency issues with protocol switching technique embedded in the router engine itself. The approach is based on hardware coding to reduce the impact of latency issues as the hardware itself is designed according to the need. We attempt to provide a multipurpose networking router by means of Verilog code, thus we can maintain the same switching speed with more security we embed the packet storage buffer on chip and generate the code as self-independent VLSI based router. Our main focus is the implementation of hardware IP .router. The approach enables the router to process multiple incoming IP packets with different versions of protocols simultaneously, e.g. for IPv4 and IPv6. The approach will results in increased switching speed of routing per packet for both current trend protocols, which we believe would result inconsiderable enhancement in networking systems.

Other Details

Paper ID: IJSRDV1I9002
Published in: Volume : 1, Issue : 9
Publication Date: 01/12/2013
Page(s): 1694-1697

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