Design and Implementation of sense amplifier based flip Flop for high performance in CMOS 45nm technology parameter |
Author(s): |
| Bhumi Jayendrasinh Vasandia , M.Tech (Purs.) CGPIT, Maliba Campus, UTU; Prof. Rakesh Gajre, M.Tech, Nirma University,Ahmedabad |
Keywords: |
| CMOS, BPTM, CSAFF, NIKOLIC |
Abstract |
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This paper will demonstrate the sense amplifier based flip flop design using static or conventional CMOS and NIKOLIC latch based topologies. Implementation is done using BPTM 45nm deep submicron technology parameter in LT spice IV. Sense amplifier plays important role in memory read and write operation which will reduce the power consumption and propagation delay. I have designed D flip flop with both logic topologies and results found a lesser power consumption and propagation delay in NIKOLIC architecture compared to conventional sense amplifier based flip flop. |
Other Details |
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Paper ID: IJSRDV2I1068 Published in: Volume : 2, Issue : 1 Publication Date: 01/04/2014 Page(s): 510-512 |
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