Review of Low Power Testing Techniques |
Author(s): |
| Dhara Desai , M.Tech.(Purs.), CGPIT,Bardoli; Dhara Desai , M.Tech.(Purs.), CGPIT,Bardoli; Prof. Rakesh Gajre , M.tech. Nirma University,Ahmedabad |
Keywords: |
| testing techniques , low power testing |
Abstract |
|
the circuit consumes more power during test mode compared to functional mode. So test power has been major big concern in large System-on-Chip designs from last decade. In this review paper, the state-of-the-art in low power testing is presented. The paper contains the detailed survey on various power reduction techniques proposed for both the aspects of testing i.e. external testing as well as Built-In-Self-Test. The advances in DFT techniques emphasizing low power are also included in this survey paper. |
Other Details |
|
Paper ID: IJSRDV2I1069 Published in: Volume : 2, Issue : 1 Publication Date: 01/04/2014 Page(s): 318-322 |
Article Preview |
|
|
|
|
