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Design of Vedic Multiplier for DSP Application

Author(s):

Archan Patel , S.P.B.Patel Engineering college; Dipal Patel, S.P.B.Patel Engineering college

Keywords:

Very high speed integrated circuit (VHSIC); VHSIC hardware description language (VHDL); Vedic Mathematics; Vedic Multiplier; Urdhva –Tiryakbyham (UT)

Abstract

this paper presents a delay comparison of two methods multipliers for unsigned data, one uses a simple multiplication and the second one uses a Vedic multiplication. The 64×64 Vedic multiplier module using Urdhva Tiryakbyham Sutra uses 2×2 Vedic multiplier modules. Urdhva tiryakbyham Sutra is most powerful Sutra, giving minimum delay for multiplication of all types of numbers, either small or large. Urdhva Tiryagbhyam– Vedic method for multiplication which strikes a difference in the real process of multiplication itself. It causes parallel generation of intermediate products, removes unwanted multiplication steps with zeroes and scaled to higher bit levels. The paper’s main focus is on the speed/delay of the multiplication operation on 64-bit multipliers which are modeled using VHDL, A hardware description language. The 64×64 Vedic multiplier is coded in VHDL, synthesized and simulated using Xilinx ISE 13.4 software. This multiplier is implemented on Spartan 3E FPGA device XC3S1600e-5fg484. The performance evaluation results in terms of speed and delay. The multiplier of Vedic multiplication has shown a less delay over the simple multiplier. The simple multiplier uses time = 153.441ns, while the Vedic multiplier with the uses time = 129.181ns on Spartan 3E device.

Other Details

Paper ID: IJSRDV2I1117
Published in: Volume : 2, Issue : 1
Publication Date: 01/04/2013
Page(s): 265-267

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