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Low Area and High Speed Vedic Mathematics Multiplier using Compressor


S.Udaya Kumar , prathyusha institute of technology and management; D.Sasirekha, prathyusha institute of technology and management; D.L Jayanthi, prathyusha institute of technology and management


urdhwa tiryakbhyam sutra, 4:2 compressor, 5:2 compressor, 7:2 compressor


There is a growing demand for high speed processing and low area design for VLSI and Communication applications in recent days. The integral part of the processor is the multiplier. The multiplier is designed using compressors. The compressors used are 4:2, 5:2, 7:2 compressors. The compressors are designed using full adder and half adder. The multiplier design is based on Urdhwa Tiryakbhayam sutra. The developed model is designed using microwind and DSCH software. The proposed multiplier has reduces the area and power consumption.

Other Details

Paper ID: IJSRDV2I12062
Published in: Volume : 2, Issue : 12
Publication Date: 01/03/2015
Page(s): 118-121

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