Design of an Efficient Sequential NANO-RAM Circuit Using Reversible Gates

we proposed the Reversible logic, it is emerging technique for decrease the energy consumption for low power VLSI application such as QCA nanotechnology and many other computing technique. In existing large number of works done in irreversible combinational logic, but the design of combinational circuits power dissipation was high, to overcome this sequential reversible circuits designed by using flip flops, latches and combinational gates. The main purpose of designing reversible logic is to decrease the quantum cost, number of garbage ouputs.in this paper we have proposed a new reversible Nano-RAM circuit that is parity preserving reversible RAM circuit .The new reversible gates are Feynman double gate, new fault tolerant, memory cells, the proposed double edge triggered flip flop is compared with existing flip flops and its efficiency shown in power, gate count, garbage output. The simulation is verified using Xilinx 8.1 and implemented in FPGA.