Floating Point Unit(FPU) for FPGAs |
Author(s): |
NIKHIL SS , TKM Instituite of Technology, Kollam, Kerala; NIKHIL SS, TKM Instituite of Technology, Kollam, Kerala; SHEELA DEVI ASWATHY CHANDRAN, TKM Instituite of Technology, Kollam, Kerala |
Keywords: |
FPGA, FPU, Normalization |
Abstract |
Floating point describes a method of representing an approximation of a real number in a way that can support a wide range of values. The numbers are in general, represented approximately to a fixed number of significant digits (the mantissa) and scaled using an exponent. The base for the scaling is normally 2, 10 or 16. Floating point arithmetic and logic unit require many algorithms. Then again, many scientific applications require floating point arithmetic because of high accuracy in their calculations. FPGAs are becoming more suitable for supporting high speed floating point arithmetic units. Floating point units are widely used in digital applications such as digital signal processing, digital image processing and multimedia. Many algorithms depend on floating point arithmetic because floating point representation supports huge range. So many algorithms are used to define the arithmetic operations such as Addition, Subtraction, Multiplication and Division. In top-down design approach, four arithmetic modules, addition, subtraction, multiplication and division are combined to form a floating point arithmetic unit and the logical operations such as logic gates and shifting operations are combined together to form logic unit. For the synthesis and simulation Xilinx 13.2 is required. |
Other Details |
Paper ID: IJSRDV2I1231 Published in: Volume : 2, Issue : 1 Publication Date: 01/04/2014 Page(s): 613-617 |
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