Low Power Design of Counter Using DDFF and Dual Mode Logic

Reducing power consumption in very large scale integrated circuits (VLSI) design has become an interesting research area. To reduce the power a new dual dynamic node hybrid flip-flop (DDFF) and an embedded logic module (DDFF-ELM) based on DDFF are used here. Both of them eliminate the drawbacks of existing high performance flip-flop designs. The proposed design mainly reduces the power consumption by eliminating the large capacitance present in the pre-charge node of several existing flip-flop designs by separately driving the output pull-up and pull-down transistors by following split dynamic node structure. This reduces the power consumption up to 40% compared to conventional architectures of flip-flops. The DDFF and DDFF-ELM are compared with other flip-flop designs by implementing in a Johnson up-down counter. The DML is introduced in Johnson counter to improve the speed performance by allowing the system to switch between static and dynamic modes of operation according to its requirements.