Design and Implementation of a Packet Switched Dynamic Buffer Resize Router on FPGA |
Author(s): |
| VIVEK RAJ K , SJCIT; PRASAD KUMAR, SJCIT; SHASHI RAJ K, DSCE |
Keywords: |
| Network on chip, wormhole router, flow control, interconnect, FSM, FPGA, LUT, GALS, Adaptive buffers, FIFO, Packets. |
Abstract |
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NoC designs are based on a compromise of latency, power dissipation or energy, usually defined at design time. However, setting all parameters at design time can cause either excessive power dissipation (originated by router underutilization), or a higher latency. The situation worsens whenever the application changes its communication pattern. In this paper we propose an FPGA based, single cycle, low latency router design that can be reconfigured to 1-D and 2-D network on chip architectures with dynamic buffer resize technique. The results show that the technique improves the area and the performance of the architecture by greatly reducing power consumption and latency between the routers. |
Other Details |
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Paper ID: IJSRDV2I2095 Published in: Volume : 2, Issue : 2 Publication Date: 01/05/2014 Page(s): 150-154 |
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