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A New Dual Stack Transistor for Ground Bounce and Leakage Current Reduction


Priyanka Singhal , BSAITM, Faridabad, Haryana; Nidhi Raghav, Lecturer, BSAITM; Pallavi Bahl, Lecturer, BSAITM


Dual Stack Transistor, Leakage Current, Ground Bounce


In this paper the author have discussed the trade-off between current CMOS technology scaling and static power consumption issues. This power consumption is an important concern for designing a low power integrated circuit. This paper has discussed different approaches for a low power integrated circuit design using leakage power reduction techniques. The main focus is on dual stack power gating approach which reduces the leakage power near about 75% in comparison to base design without the power gating structure at 90 nm technology

Other Details

Paper ID: IJSRDV2I3009
Published in: Volume : 2, Issue : 3
Publication Date: 01/06/2014
Page(s): 93-95

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