BEHAVIORAL MODELING AND VHDL SIMULATION OF AN ALL DIGITAL PHASE LOCKED LOOP |
Author(s): |
| Vikas Gaur , JSS academy of technical education, Noida; Vikas Gaur, JSS academy of technical education, Noida; Gayatri Sakya, JSS academy of technical education, Noida |
Keywords: |
| VHDL, PLL, CORDIC |
Abstract |
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In this paper, we have designed a model of an all-digital phase-locked loop (ADPLL) which is discrete in nature. The design is carried out in simulink and then the code of the main blocks i.e. DDS and Hilbert is written and verified in VHDL. The basic components of the ADPLL are the phase detector, the loop filter and voltage controlled oscillator which is realized as the direct digital synthesizer (DDS).The phase detection is realized by using the Hilbert transform and then the phase is calculated using CORDIC algorithm. The linear range of the ADPLL is increased by using the phase-unwrap block. All equations to design this ADPLL are derived by using the relations of time continuous PLL. The time continuous model is simulated first by using matlab-simulink and all equations are analyzed. By using these equations all the relations to design an all-digital PLL are obtained. |
Other Details |
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Paper ID: IJSRDV2I3109 Published in: Volume : 2, Issue : 3 Publication Date: 01/06/2014 Page(s): 100-103 |
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