Verification of SHA Crypto Processor Core |
Author(s): |
| Ketankumar Jayantilal Dhimmar , Gujarat Technological University PG School, Ahmedabad; Ritesh Maheshbhai Pankhaniya, Gujarat Technological University PG School, Ahmedabad |
Keywords: |
| Secure hash Algorithm, Test Bench, Test plan, Test case, Randomization, Regression, Coverage |
Abstract |
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This paper verifies the Secure Hash Algorithm (SHA) Crypto Processor Core by applying different types of test cases as input. The test cases are given as randomized which will more efficient to catch the bug from design compare to direct test. As there are so many versions of SHA algorithm like SHA-1, SHA-2(160, 256, 384 and 512) and also now SHA-3, this paper verifies the 256 bit SHA algorithm. The verification of core is done using System Verilog language. The tool used for verification is questasim 6.6d by Mentor Graphics. |
Other Details |
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Paper ID: IJSRDV2I3132 Published in: Volume : 2, Issue : 3 Publication Date: 01/06/2014 Page(s): 285-288 |
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