Design and Implementation of 6-bit Successive Approximation Register (SAR) Analog to Digital Convertor (ADC) Using 45 Nano-meter Technology. |
Author(s): |
| NIRAV A. MEHTA , CCET, WADHWAN, SURENDRANAGAR; Prof. B. H. NAGPARA, CCET, WADHWAN, SURENDRANAGAR |
Keywords: |
| CMOS, Sample and Hold, Comparator, SAR Logic, DAC Logic, TANNER TOOL |
Abstract |
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In this paper, The Design and Implementation of Successive Approximation Register (SAR) Analog to Digital Convertor (ADC) in 45 nm technology using TANNER TOOL, V15 is presented. The simulation results show the transient analysis waveforms of different blocks of SAR ADC and also the result of 6-bit SAR ADC. The mainly four blocks are in the SAR ADC. The blocks are Sample and Hold, Dynamic Comparator, SAR Logic and DAC Logic. Here the DAC logic is used for the feedback to comparator and its made from the charge scaling capacitor. This design is for low power and low area consumption in chip or circuit design and compared with each other. These SAR ADC is high speed switching and low power consumption with compares to any other ADC. |
Other Details |
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Paper ID: IJSRDV2I3184 Published in: Volume : 2, Issue : 3 Publication Date: 01/06/2014 Page(s): 15-18 |
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