Faults in Digital VLSI Circuits |
Author(s): |
| Sandeep Kumar Ojha , St. Andrews Institute of Technology & Management |
Keywords: |
| SBTPG, IC manufacturer, Digital circuit, Stuck-at faults, ATPG, PCB, MCM, ECL, TTL, CMOS |
Abstract |
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In considering the techniques that may be used for digital circuit testing, two distinct philosophies may be found, First is Functional Testing, which undertake a series of functional tests and check for the correct (fault free) 0 or 1 output response. It does not consider how the circuit is designed, but only that it gives the correct output during test and second one is Fault Modelling in whichto consider the possible Faults that may occur within the circuit, and then to apply a series of tests which are specifically formulated to check whether each of these faults is present or not.The faults which are likely to occur on the wafer during the manufacture of the ICs, and compute the result on the circuit output(s) with or without each fault present. Each of the final series of tests is then designed to show that a particular fault is present or not. |
Other Details |
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Paper ID: IJSRDV2I7013 Published in: Volume : 2, Issue : 7 Publication Date: 01/10/2014 Page(s): 3-5 |
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