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FPGA Implementation of Viterbi Decoder using Hybrid Trace Back and Register Exchange Method

Author(s):

Gaurav Suman , Takshshila Institute of Engineering and Technology; Pravin Tiwari, Takshshila Institute of Engineering and Technology

Keywords:

Viterbi Decoder, Trace Back, Register Exchange, FPGA, VHDL, Xilinx, XST, Virtex4

Abstract

Error correction is an integral part of any communication system and for this purpose, the convolution codes are widely used as forward error correction codes. For decoding of convolution codes, at the receiver end Viterbi Decoder is being employed. The parameters of Viterbi algorithm can be changed to suit a specific application. The high speed and small area are two important design parameters in today’s wireless technology. In this paper, a high speed feed forward viterbi decoder has been designed using hybrid track back and register exchange architecture and embedded BRAM of target FPGA. The proposed viterbi decoder has been designed with Matlab, simulated with Xilinx ISE 8.1i Tool, synthesized with Xilinx Synthesis Tool (XST), and implemented on Xilinx Virtex4 based xc4vlx15 FPGA device. The results show that the proposed design can operate at an estimated frequency of 107.7 MHz by consuming considerably less resources on target device to provide cost effective solution for wireless applications.

Other Details

Paper ID: IJSRDV2I7066
Published in: Volume : 2, Issue : 7
Publication Date: 01/10/2014
Page(s): 135-137

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